Xiyuan Tang | Sun Research Group

Latest

A 0.004-mm2 200MS/s Pipelined SAR ADC with kT/C Noise Cancellation and Robust Ring-Amp
A 0.014mm2 10kHz-BW Zoom-Incremental-Counting ADC Achieving 103dB SNDR and 100dB Full-Scale CMRR
An Overview of Noise-Shaping SAR ADC: From Fundamentals to the Frontier
10.4 A 3.7mW 12.5MHz 81dB-SNDR 4th-Order CTDSM with Single-OTA and 2nd-Order NS-SAR
27.1 A 250kHz-BW 93dB-SNDR 4th-Order Noise-Shaping SAR Using Capacitor Stacking and Dynamic Buffering
27.4 A 0.4-to-40MS/s 75.7dB-SNDR Fully Dynamic Event-Driven Pipelined ADC with 3-Stage Cascoded Floating Inverter Amplifier
A 77.1-dB-SNDR 6.25-MHz-BW Pipeline SAR ADC With Enhanced Interstage Gain Error Shaping and Quantization Noise Shaping
A 13.5-ENOB, 107-μW Noise-Shaping SAR ADC With PVT-Robust Closed-Loop Dynamic Amplifier
A 13-bit 0.005-mm2 40-MS/s SAR ADC With kT/C Noise Cancellation
A 74.5-dB Dynamic Range 10-MHz BW CT-ΔΣ ADC With Distributed-Input VCO and Embedded Capacitive-π Network in 40-nm CMOS
An Energy-Efficient Time-Domain Incremental Zoom Capacitance-to-Digital Converter
16.5 A 13b 0.005mm2 40MS/s SAR ADC with kT/C Noise Cancellation
9.3 A 40kHz-BW 90dB-SNDR Noise-Shaping SAR with 4× Passive Gain and 2nd-Order Mismatch Error Shaping
9.5 A 13.5b-ENOB Second-Order Noise-Shaping SAR with PVT-Robust Closed-Loop Dynamic Amplifier
An Energy-Efficient Comparator With Dynamic Floating Inverter Amplifier
A 0.025-mm2 0.8-V 78.5-dB SNDR VCO-Based Sensor Readout Circuit in a Hybrid PLL-ΔΣ M Structure
A Fractional- N PLL With Space–Time Averaging for Quantization Noise Reduction
A Second-Order Purely VCO-Based CT ΔΣ ADC Using a Modified DPLL Structure in 40-nm CMOS
A 10-bit 120-MS/s SAR ADC With Reference Ripple Cancellation Technique
A Two-Step ADC With a Continuous-Time SAR-Based First Stage
18.2 A 16fJ/Conversion-Step Time-Domain Two-Step Capacitance-to-Digital Converter
3.4 A 0.01mm2 25µW 2MS/s 74dB-SNDR Continuous-Time Pipelined-SAR ADC with 120fF Input Capacitor
A 10-b 800-MS/s Time-Interleaved SAR ADC With Fast Variance-Based Timing-Skew Calibration
A 0.7-V 0.6-μW 100-kS/s Low-Power SAR ADC With Statistical Estimation-Based Noise Reduction
A 74.5-dB Dynamic Range 10-MHz BW CT-ΔΣ ADC With Distributed-Input VCO and Embedded Capacitive-π Network in 40-nm CMOS