Linxiao Shen

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An Overview of Noise-Shaping SAR ADC: From Fundamentals to the Frontier
10.4 A 3.7mW 12.5MHz 81dB-SNDR 4th-Order CTDSM with Single-OTA and 2nd-Order NS-SAR
27.7 A 79dB-SNDR 167dB-FoM Bandpass ΔΣ ADC Combining N-Path Filter with Noise-Shaping SAR
A 13.5-ENOB, 107-μW Noise-Shaping SAR ADC With PVT-Robust Closed-Loop Dynamic Amplifier
A 13-bit 0.005-mm2 40-MS/s SAR ADC With kT/C Noise Cancellation
A 74.5-dB Dynamic Range 10-MHz BW CT-ΔΣ ADC With Distributed-Input VCO and Embedded Capacitive-π Network in 40-nm CMOS
An Energy-Efficient Time-Domain Incremental Zoom Capacitance-to-Digital Converter
16.5 A 13b 0.005mm2 40MS/s SAR ADC with kT/C Noise Cancellation
9.5 A 13.5b-ENOB Second-Order Noise-Shaping SAR with PVT-Robust Closed-Loop Dynamic Amplifier
An Energy-Efficient Comparator With Dynamic Floating Inverter Amplifier
A 0.025-mm2 0.8-V 78.5-dB SNDR VCO-Based Sensor Readout Circuit in a Hybrid PLL-ΔΣ M Structure
A Second-Order Purely VCO-Based CT ΔΣ ADC Using a Modified DPLL Structure in 40-nm CMOS
A 10-bit 120-MS/s SAR ADC With Reference Ripple Cancellation Technique
A Two-Step ADC With a Continuous-Time SAR-Based First Stage
18.2 A 16fJ/Conversion-Step Time-Domain Two-Step Capacitance-to-Digital Converter
3.4 A 0.01mm2 25µW 2MS/s 74dB-SNDR Continuous-Time Pipelined-SAR ADC with 120fF Input Capacitor
A 1-V 0.25-μW Inverter Stacking Amplifier With 1.07 Noise Efficiency Factor
A 74.5-dB Dynamic Range 10-MHz BW CT-ΔΣ ADC With Distributed-Input VCO and Embedded Capacitive-π Network in 40-nm CMOS