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Arindam Sanyal

A Fractional- N PLL With Space–Time Averaging for Quantization Noise Reduction
An Energy-Efficient Hybrid SAR-VCO ΔΣ Capacitance-to-Digital Converter in 40-nm CMOS
A 0.7-V 0.6-μW 100-kS/s Low-Power SAR ADC With Statistical Estimation-Based Noise Reduction

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